Due to recent further increases in integration and processing speed of LSI (Large-Scale Integration), problems caused by changes in LSI power sources or ground potential have been increasing. In order for an LSI circuit to be operated, a power source for applying a high potential and a ground for applying a low potential are required.
FIGS. 13A and 13B are diagrams illustrating the relation between an inverter circuit of a CMOS, its signal output, and a change in power source and ground potential. When the output of the CMOS inverter configured as shown in FIG. 13A switches from a low level to a high level, the NMOS 805 side is closed and the PMOS 804 side is opened. Consequently, charging current 807 is produced such that charges accumulated in a power source 802 pass through the PMOS 804 and accumulate in a load 806. At the instant when this switching from the low to high level takes place, the charges are released from a power source conductor and a spike noise consequently occurs such that the power source potential momentarily decreases.
In addition, when the output of the CMOS inverter switches from a high level to a low level, discharge current 808 is produced such that the PMOS 804 side is closed, the NMOS 805 side is opened, and charges accumulated in the load 806 flow into the ground 803 through the NMOS 805. At the instant when this switching from high to low level takes place, charges flow from the load 806 into the ground 803, with the result that the ground potential momentarily increases and hence so-called the spike noise is generated.
Accordingly, at the time of a clock output 809, a spike noise occurs in a power source potential waveform 810 and also in a ground potential waveform 811 such that the directions of the noises are alternately opposite to each other. The circuit is operated by the difference between the power source potential and the ground potential. Accordingly, the potential difference that the circuit receives is affected by a spike noise 812 with a periodicity of half the clock. Such changes in potential cause, for example, erroneous operations of an LSI or changes in output timing of a signal.
As disclosed in Japanese Patent Application Laid-Open No. 2006-261470, recent LSIs have generally been designed such that a capacitive component, such as a bypass capacitor, is disposed between the power source and the ground. As shown in FIG. 14A, a capacitor 814 disposed to prevent the above-mentioned problems causes decrease in the ground potential, which follows the decrease in the power source 802 potential which is caused upon the switching. This makes changes in the power source potential waveform 815 and those in the ground potential waveform 816 coincide as shown in FIG. 14B. Accordingly, the potential difference 817 between the power source and the ground is greatly reduced.
However, a bypass capacitor disposed on a printed wiring board only reduces the noise arising from the differential between the power source and ground. It is actually difficult to ensure an ideal ground and hence impossible to suppress a common mode noise in which the potentials of the power source and ground change in the same phase even when the bypass capacitor is used.
Like the differential mode noise, the common mode noise is emitted into the space, with a power source conductor and ground conductor as antennas, and increase radiation noise becomes increase radiation noise.
As a means for reducing the common mode noise, a technology has been proposed in which a ferrite core is attached to a printed wiring board and the common mode noise is converted into heat. However, in order to obtain this effect in a required frequency band, the ferrite core needs to have a certain degree of capacitance. In addition, since the ferrite core is of a sintered body, it is difficult to produce small ferrite cores. In addition, the ferrite core needs to be disposed in a plurality of areas where noise is to be restrained. Accordingly, this is not an effective means in terms of cost either.
A technique for reducing a common mode noise generated in two conductors is proposed in US 2006/0125570. According to this document, center tap termination is constituted such that two signal conductors in differential signal transmission are connected by two capacitors connected in series between the signal conductors and the ground and a junction point of the two capacitors is connected by a resistor.
However, this technique is designed to reduce a common mode noise relative to differential signals, and cannot cope with a common mode noise arising from the power source and ground of a DC circuit. Specifically, in the case of a DC circuit as shown in FIG. 13A, a common mode noise flows in the same direction in power source wiring and ground wiring. Accordingly, the center tap termination as shown in FIG. 14A is not applicable. To be specific, since the common mode noise arises between the power source and the ground, a ground connected through a resistor is not included in the circuit.
It is known that such common mode noise arising between the power source and ground may cause considerable radiation noise even with slight current. Therefore, on account of higher speed LSIs, it has recently become important to reduce radiation noise caused by the common mode noise arising from between the power source and ground.